Gate depletion issues, high gate resistance, high gate tunneling currents, and boron penetration into a channel are problems encountered when heavily doped polysilicon gates of conventional CMOS transistors are shrunk. Some of these problems can be eliminated or greatly reduced by use of metal gates. A metal gate eliminates polysilicon gate depletion and boron penetration from the polysilicon into the channel, and also reduces the gate sheet resistance.
However, simply replacing the polysilicon gate with a metal gate is not generally possible, in part because of the different required gate work function for effective operation of PMOS and NMOS transistors. To control short channel effects and keep off-current low, a higher than poly gate work function is required for NMOS and a lower than p+ poly gate work function is required for PMOS, Switching between a polysilicon gate work function suitable for a PMOS transistor and one suitable for an NMOS transistor requires only a minor change to the polysilicon dopant implant process. In contrast, if a mid-gap metal having a work function intermediate to the PMOS and NMOS transistors is selected as a gate metal, a transistor designer must deal with a high threshold voltage. For example, a mid-gap metal having work function around silicon's mid gap value of about 4.6 eV could be selected to provide symmetric benefit to both PMOS and NMOS transistors. Such work function would result in threshold voltages too high to be acceptable for high performance logic applications, unless costly multiple metal post-processing or alloying is used to differentiate the PMOS and NMOS gate work functions.
Because of such problems, transistor designers have utilized two metals having differing work functions that are respectively appropriate for PMOS and NMOS transistors. For example, a conventional high-k/metal gate implementation can utilize a metal that works for NMOS (typically with a work function between 4.05 eV and 4.6 CV) and a metal that works with PMOS (typically of work function between 4.6 eV and 5.2 eV). Common NMOS metals include tantalum silicon nitride (TaSiN), titanium nitride (TiN), or tantalum nitride (TaN), all of which have a work function close to the silicon conduction band. PMOS metals include ruthenium (Ru), molybdenum (Mo), or tungsten (W), all of which have work functions close to the silicon valence band.
While dual metal gate transistors can be produced cost effectively for die composed of a single device transistor type, the situation is not as clear for complex a system-on-a-chip (SoC) die having multiple transistor types. A system-on-a-chip die can require multiple types of digital and analog transistors to handle low and high speed logic, memory, wireless, and input/output functions. Each device type may have a different required set of PMOS and NMOS gate metals for optimal operation. If only two metals are used for all device types, performance compromises must be made, and certain types of devices may be incompatible with each other. However, requiring expensive additional masking and processing steps to deposit multiple sets of gate metal for each device type is costly, time-consuming, and results in increased failure rate.